1. Field of the Invention
The present invention relates generally to a phase-locked loop (PLL), and more specifically to a PLL using a random access memory.
2. Description of the Related Art
It is known in the art that a PLL is essentially a closed loop electric servomechanism whose output is locked onto, and will track a reference signal.
Before turning to the present invention, it is deemed advantageous to briefly describe, with reference to FIG. 1, a conventional PLL.
A PLL 10, shown in FIG. 1, is comprised of a phase detector 12, a control voltage generator 14, a voltage-controlled oscillator (VCO) 16, and a frequency divider (or frequency demultiplier) 18. A reference clock CLK0 is fed to the phase detector 12 which also receives a clock CLK2 from the frequency divider 18. The phase detector 12 compares the phases of the two clocks CLK0 and CLK2, and generates an error signal which is proportional to the phase difference between the two clocks. Although not shown in FIG. 1, the error signal is typically filtered by a loop filter (low-pass filter) and is applied to the control voltage generator 14 whose output is adjusted to generate a clock CLK1 from the VCO 16 with a predetermined clock rate (frequency). The clock CLK1 is applied to an external circuit (not shown) and to the frequency divider 18. Assuming that a divide value of the frequency divider 18 is Nv, then the frequency of the clock CLK1 is expressed by Nv multiplied by the frequency of the reference clock CLK0.
The above-mentioned conventional PLL has failed to pay any attention to the quality of the reference clock CLK0. In other words, the PLL of FIG. 1 is unable to determine the quality of the reference clock CLK0. Therefore, the PLL of FIG. 1 has suffered from the following difficulties. That is, the output clock CLK1 is undesirably deteriorated in the case where the clock rate of the reference clock CLK0 becomes unstable, and in the case where the wave-form of the reference clock CLK0 is disturbed due to noises superimposed thereon, and in the case where the reference clock CLK0 is instantaneously terminated.